Miniaturization of integrated circuit (IC) devices demands superior electrical properties from both dielectric and conductive materials used in the manufacturing of an integrated circuit. Traditionally used materials, such as aluminum as a conductor and silicon dioxide as an insulator no longer provide adequate electrical characteristics at the modern level of miniaturization. Therefore, the manufacturers of IC devices are now employing new dielectric materials with lower dielectric constant than silicon dioxide and are increasingly turning to copper as a conductor, due to its low resistivity. The low-k dielectric materials used in the IC device processing include carbon doped silicon dioxide, hydrogenated silicon oxycarbides (SiCOH), fluorine doped silicon dioxide, and organic-containing low-k dielectrics. These materials, due to their low dielectric constants, provide low parasitic capacitance and minimize the “crosstalk” between the interconnects in an integrated circuit. At the same time, they are often porous foam-like materials and are generally more easily damaged during the processing steps than silicon dioxide. The impact of high-energy ions during such processing steps as PVD often results in undesired etching and microtrenching in the low-k dielectric layer. This problem is usually less pronounced when silicon dioxide is used.
The use of copper as a conductor, in addition to an obvious benefit of better conductive properties, also gives rise to several problems which are obviated by using a different processing technique than one traditionally employed with aluminum. One of these problems is a facile diffusion of copper into the adjacent dielectric layer. This diffusion results in a degradation of the insulating properties of a dielectric even at very low concentrations. This problem is solved by using a diffusion barrier layer between copper lines and a dielectric. Another problem in processing copper-containing ICs is that copper is not amenable to patterning by plasma etching. This can be obviated by using Damascene processing, a method which requires fewer processing steps than other methods and offers a higher yield.
Damascene processing is a method for forming interconnections on integrated circuits. It involves formation of inlaid metal lines in trenches and vias formed in a dielectric layer (inter-metal dielectric). In order to frame the context of this invention, a brief description of a copper dual Damascene process for forming a partially fabricated integrated circuit is described below. Note that the invention applies to other fabrication processes including single Damascene processes.
Presented in FIGS. 1A-1F, is a cross sectional depiction of device structures created at various stages of a dual Damascene fabrication process. A cross sectional depiction of a completed structure created by the dual Damascene process is shown in FIG. 2. Referring to FIG. 1A, an example of a typical substrate, 100, used for dual Damascene fabrication is illustrated. Substrate 100 includes a pre-formed dielectric layer 103 (such as fluorine or carbon doped silicon dioxide or organic-containing low-k materials) with etched line paths (trenches and vias) in which a diffusion barrier 105 has been deposited followed by inlaying with copper conductive routes 107. Because copper or other mobile conductive material provides the conductive paths of the semiconductor wafer, the underlying silicon devices must be protected from metal ions (e.g., Cu2+) that might otherwise diffuse or drift into the silicon. Suitable materials for diffusion barrier 105 include tantalum, tantalum nitride, tungsten, titanium tungsten, titanium nitride, tungsten nitride, cobalt, ruthenium and the like. In a typical process, barrier 105 is formed by a physical vapor deposition (PVD) process such as sputtering, a chemical vapor deposition (CVD) process, or an atomic layer deposition (ALD) process. Typical metals for the conductive routes are aluminum and copper. More frequently, copper serves as the metal in Damascene processes, as depicted in these figures. The resultant partially fabricated integrated circuit 100 is a representative substrate for subsequent Damascene processing, as depicted in FIGS. 1B-1F.
As depicted in FIG. 1B, a silicon nitride or silicon carbide diffusion barrier 109 is deposited to encapsulate conductive routes 107. Next, a first dielectric layer, 111, of a dual Damascene dielectric structure is deposited on diffusion barrier 109. This is followed by deposition of an etch-stop layer 113 (typically composed of silicon nitride or silicon carbide) on the first dielectric layer 111.
The process follows, as depicted in FIG. 1C, where a second dielectric layer 115 of the dual Damascene dielectric structure is deposited in a similar manner to the first dielectric layer 111, onto etch-stop layer 113. Deposition of an antireflective layer 117, typically a silicon oxynitride, follows.
The dual Damascene process continues, as depicted in FIGS. 1D-1E, with etching of vias and trenches in the first and second dielectric layers. First, vias 119 are etched through antireflective layer 117 and the second dielectric layer 115. Standard lithography techniques are used to etch a pattern of these vias. The etching of vias 119 is controlled such that etch-stop layer 113 is not penetrated. As depicted in FIG. 1E, in a subsequent lithography process, antireflective layer 117 is removed and trenches 121 are etched in the second dielectric layer 115; vias 119 are propagated through etch-stop layer 113, first dielectric layer 111, and diffusion barrier 109.
Next, as depicted in FIG. 1F, these newly formed vias and trenches are, as described above, coated with a diffusion barrier 123. As mentioned above, barrier 123 is made of tantalum, or other materials that effectively block diffusion of copper atoms into the dielectric layers.
After diffusion barrier 123 is deposited, a seed layer of copper is applied (typically a PVD process) to enable subsequent electrofilling of the features with copper inlay. FIG. 2 shows the completed dual Damascene process, in which copper conductive routes 125 are inlayed (seed layer not depicted) into the via and trench surfaces over barrier 123.
Copper routes 125 and 107 are now in electrical contact and form conductive pathways, as they are separated only by diffusion barrier 123, which is also somewhat conductive. Traditionally these diffusion barriers are deposited using PVD methods because of the high quality resultant films. However, when depositing in features with higher aspect ratios such as the narrow vias within modern technologies, PVD methods tend to produce films with poor sidewall coverage and thick bottom coverage.
Therefore there is a need for a method that would remove some of the barrier layer from the via bottom and would increase the coverage of the via sidewalls. It is also sometimes desirable to remove all of the barrier layer from the via bottom, and even etch out some of the underlying copper layer, while maintaining the sidewall coverage. Ideally, this method should be selective for the via bottom region, and should not affect the trenches. However, good selectivity cannot be achieved in currently available methods. Therefore it is preferable, that any such method employed should cause the least possible damage in the trenches, while removing the material from the via bottom.